This invention relates to testing digital electronic circuits, and is particularly, although not exclusively concerned with testing large scale integrated (LSI) circuits.
A digital circuit can generally be considered as consisting of a number of data storage elements (e.g. bistable circuits) interconnected by a combinational logic network (e.g. AND gates, OR gates and so on). The testing of such circuits can be very complex, especially if the circuit is an LSI chip, which makes it difficult to gain access to the storage elements within the chip.
British Patent Specification No. 1,546,147 describes a digital electronic circuit having a diagnostic mode in which the data storage elements are connected together in series to act as a shift register. This allows test patterns to be shifted serially into the storage elements, and the results of test sequences to be shifted out serially for analysis. This can greatly ease the problem of testing an LSI chip, since it provides access to internal registers on the chip which would otherwise be inaccessible. Since the test patterns and results are shifted serially, the number of extra terminals required for testing is minimised.
However, if the number of storage elements in the circuit is large, it may take an excessively long time to shift data through the shift register, and hence testing will be a slow process. This problem is particularly severe when it is required to test LSI chips during or after manufacture, when it is desirable to perform the tests as quickly as possible.
One object of the present invention is therefore to reduce the time required for testing a digital electronic circuit.